1. Field of the Invention
This invention relates to an improvement in integrated circuit layouts. More particularly, it pertains to a layout scheme for integrated circuits in which alteration of the circuit operating characteristics produced as a result of mechanical stresses imposed by packaging a semiconductor substrate including the integrated circuit are minimized. Most especially, it relates to a layout scheme in which certain critical circuit elements, the performance of which is altered by mechanical stress, are positioned in a semiconductor substrate including them in such a manner as to minimize the effect on overall circuit performance of the alteration of performance characteristics of the circuit elements produced by mechanical stress.
2. Description of the Prior Art
It is known to provide certain kinds of symmetry in integrated circuit layouts for certain purposes. For example, Agusta et al, U.S. Pat. No. 3,508,209 teaches the use of vertical, horizontal and diagonal symmetry for space-saving purposes in the layout of memory array integrated circuits.
Solomon, "The Monolothic Op Amp, A Tutorial Study," IEEE Journal of Solid State Circuits, Volume SC-9, No. 6, December 1974, discloses the provision of operational amplifier input transistors on isothermal lines of an integrated circuit substrate in order to increase the maximum usable DC gain obtainable with the operational amplifier.
In linear integrated circuits, a matched or ratio relationship between certain circuit elements, such as resistors and transistors, is required in order to obtain desired output signals in response to predetermined input signals. If the matching or ratio relationship between these circuit elements is not maintained, the circuit may have an undesirably limited operating range or even be totally unsuited for its intended use. Such common linear integrated circuits as operational amplifiers, voltage regulators and voltage comparators are subject to this constraint.
As integrated circuit technology has become more and more sophisticated, there has been a general tendency to provide transistors making up the circuits in thinner and thinner layers. For example, a typical prior art bipolar transistor operational amplifier has transistor junction depths of about three microns. Changes due to mechanical stress in the operating characteristics of transistors formed with these junction depths have not been a serious problem in practice. However, a newer technology incorporates JFET as input devices for operational amplifier circuits. Such JFETs typically have junction depth of about 1,000 .ANG., or 0.1 micron. Metal oxide silicon (MOS) FETs are similarly surface effect devices with comparable junction depths. Transistors which are this thin are significantly more sensitive to changes in their operating characteristics due to mechanical stresses obtained while mounting a semiconductor substrate including them in a package than circuit elements with greater junction depths.
Thus, while the integrated circuit art is a well developed one, an increasing need presently exists for integrated circuits including critical stress-sensitive type circuit elements, which circuits are not sensitive to changes in their operating characteristics due to mechanical stress.